1. Field of the Invention
The present invention relates to a PLL circuit and a circuit for a reference oscillation of the PLL circuit. More particularly, the present invention relates to a method of reducing noise resulting from a harmonic component and a circuit for the same.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional PLL oscillating circuit. In FIG. 1, an oscillating circuit 17 generates an oscillation signal which is divided in frequency by a reference counter 4 into a reference signal. A voltage controlled oscillator (VCO) 1 outputs an oscillation signal which is divided in frequency by a signal counter 3 into a clock signal. The reference signal and the clock signal are supplied to a phase comparator 5. A charge pump 6 supplies an output determined based on the output of the phase comparator 5 to a low pass filter (LPF) 2. The VCO oscillates in accordance with the output of the low pass filter 2.
FIG. 2 is a block diagram illustrating the configuration of a selective call radio receiver in which the conventional PLL oscillating circuit is used as a local oscillator. A reception signal received by an antenna (ANT) 51 is amplified by an amplifier (RFAMP) 52 and is passed through a band pass filter (BPF) 53 to be supplied to a multiplier (1STMIX) 54. The output from an oscillating circuit corresponding to the oscillating circuit shown in FIG. 1 is passed through a frequency multiplying circuit 59 to be supplied to the multiplier (1STMIX) 54. The output of the multiplier 54 is passed through a band pass filter (BPF) 55 and then is supplied to a multiplier (2NDMIX) 56. An oscillation signal is supplied to the multiplier 56 from an oscillating circuit 60 corresponding to the oscillating circuit shown in FIG. 1. An output of the multiplier 56 is passed through a band pass filter (BPF) 57 and then is supplied to a demodulator (DEMOD) 58.
FIG. 3 is a diagram illustrating a Colpitts quartz oscillating circuit, and FIG. 4 is a diagram illustrating an electrically equivalent circuit of the Colpitts quartz oscillating circuit.
In order that a receiver has an excellent radio performance, it is important to reduce various noises resulting from the PLL oscillating circuit. A dead zone performance of a phase comparator, a reference leak due to a comparison frequency, a frequency performance of a low pass filter (LPF) and the like have influence on a carrier to noise ratio (C/N) of a voltage controlled oscillator (VCO), and also determines a sensitivity suppressing performance of the receiver.
Moreover, harmonic component noise in a quartz oscillating circuit or a VCO circuit causes spurious disturbances. In order to suppress the spurious disturbances. it is necessary to restrain an oscillation level of an oscillating circuit not to be excessively large and to insert filters between stages at respective circuit sections. Thus, the harmonic component noise in the oscillating circuit can be reduced.
As mentioned above, the problem is the occurrence of the harmonic component in this quartz oscillating circuit. The level of the harmonic component can be reduced if an oscillation output can be made closer to an oscillation of a sine wave. For this purpose, it is necessary to suppress an amplitude of the oscillation so that an amplitude of the output of the oscillating circuit is not limited by a voltage of a power supply or a collector saturation of a transistor.
However, if the amplitude of the quartz oscillating circuit is made lower, a start performance becomes worse, so that a lockup time of the PLL oscillating circuit becomes longer. In an apparatus having a system for performing a battery saving function, a time period between a time when the PLL oscillating circuit is turned ON and a time when the receiver is turned ON (a start of a receiving operation) is referred to as a start margin. Thus, the receiver is designed in such a manner that the lockup of the PLL oscillating circuit is completed within the start margin. A life of a battery is shortened if the start margin is set to be larger as the lockup time is made longer.
In conjunction with the above description, a PLL system offset frequency synthesizing circuit is described in Japanese Laid Open Patent Application (JP-A-Showa 62-36921). In this reference, a mixer frequency-converts an output signal from a voltage controlled oscillator based on an externally supplied RF sine signal. A first phase comparator compares the signal mixed down by the mixer with an offset frequency signal in frequency. A second phase comparator compares the output signal from the voltage controlled oscillator and the RF sine signal. A maximum value circuit selects a larger one of the output from the first phase comparator and the output from the second phase comparator and supplies the selected output as a control signal to the voltage controlled oscillator.